The present invention relates to a compound semiconductor, particularly, a Schottky gate field effect transistor using GaAs and its fabrication method. The Schottky gate field effect transistor will be referred to as MESFET (metal semiconductor field effect transistor) in the following.
Extensive efforts to develop a high frequency analog integrated circuit, e.g., MMIC (monolithic microwave IC), using GaAs MESFETs have been made at present and, in order to produce an integrated circuit that can operate in a higher frequency range at low dissipation power, the cut-off frequency f.sub.t of the MESFETs that make up the integrated circuit is desirable to be as high as possible.
For the purpose of increasing the cut-off frequency f.sub.t, efforts have so far been made to increase the transconductance gm and shorten the gate length L.sub.g of the MESFETs. Also, in order to reduce the noise figure NF that makes an important factor for the analog integrated circuits, how to reduce source resistance R.sub.s and gate resistance R.sub.g has been an important issue.
On the other hand, the recess gate FET has been so far employed as a fabrication method of the GaAs MESFETs. However, use of a wet etching method in the recess etching process that determines the electrical characteristics of the MESFETs has caused a problem in precise control and uniformity of the etching amount. So, a self-alignment structured FET originally developed for high-speed digital ICs and characterized by having a refractory metal layer with excellent uniformity used as the gate electrode has recently been actively pursued for use in high frequency analog integrated circuits.
FIGS. 3(a)-3(f) are cross-sectional illustrations of the main fabrication steps to show how the prior art GaAs MESFETs of a self-aligned LDD (Light Doped Drain) structure with refractory metal gate are produced. As shown in FIG. 3(a), a selective ion implantation of .sup.29 Si.sup.+ is first performed under the condition of an acceleration voltage of 30 keV and a dose amount of 4.times.10.sup.12 cm.sup.-2 to form a region 8 on a semi-insulating GaAs substrate 1 with resist 2 used as a mask.
Next, a layer 10 of a high melting point metal such as WSi or the like, for example, is deposited by a sputtering method on the semi-insulating GaAs substrate 1 and then, as shown in FIG. 3(b), the high melting point metal layer 10 is etched by a reactive ion etching method (RIE) and with resist 16 used as a mask to form a gate electrode 10b. Then, as shown in FIG. 3(c), an ion implantation of .sup.28 Si.sup.+ is performed under the condition of an acceleration voltage of 50 keV and a dose amount of 4.times.10.sup.12 cm.sup.-2 by a self-alignment method with resist 17 and the foregoing gate electrode 10b used as masks to form an n-type intermediate density layer 3.
Further, as shown in FIG. 3(d), an insulating layer 6 of SiN or the like is deposited on the surface of the semi-insulating substrate 1 by a plasma CVD method to a thickness of around 50 to 500 nm and then a through implantation of .sup.28 Si.sup.+ is performed under the condition of an acceleration voltage of 150 keV and a dose amount of 4.times.10.sup.13 cm.sup.-2 through an insulating layer 6 with resist 18 used as a mask to form an n-type high density layer 5.
Then, the insulating layer 6 is removed by buffered hydrogen fluoride acid and, as shown in FIG. 3(e), an insulating layer 19 of SiO.sub.2 or the like is deposited on the surface of the semi-insulating GaAs substrate 1 by a plasma CVD method or the like to a thickness of around 10 to 500 nm. Then, the implanted impurities are activated through annealing in a N.sub.2 atmosphere at around 800.degree. C. for about 15 minutes with the above insulating layer 19 used as an annealing cap. Lastly, as shown in FIG. 3(f), windows are formed in certain specified areas of the insulating layer 19 by means of buffered hydrogen fluoride acid or the like and an AuGe/Ni is deposited by a lift off technique to a thickness of around 200 nm and then sintered to form a source electrode 14 and a drain electrode 15, finally to complete a GaAs MESFET.
Thus, in connection with the fabrication method of GaAs MESFETs intended for use in high frequency analog integrated circuits, e.g. MMICs, an employment of the self-alignment structured FET has been examined for replacing the recess gate structured FET in consideration of the advantages anticipated in controllability and also uniformity of electrical characteristics.
However, the resistivity of the high melting point metal alloy layers that can be used in such a self-alignment structure will be ranging from 50 to 500 un. cm, which is 20 to 200 times as high as the resistivity of aluminum, e.g., 2.5 un.cm.
The increase in the gate resistance Rg due to the shortened gate length will become so large that it cannot be neglected and has been one of the main factors in restricting high frequency operation of an FET.
In order to solve this problem, metal such as Au or the like having a low specific resistance has been used as a deposit on the gate electrode after annealing for a reduction in the gate resistance. However, it is not easy to deposit Au on a gate electrode measuring 1 um and less with good reproductibility. Besides, the impurities implanted by a self-alignment method with a prior art gate electrode having a high melting point metal layer used as am ask tends to diffuse under the gate electrode in the lateral direction, making it difficult to produce MESFETs having a gate length not exceeding 0.5 um.